1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device which includes DRAM comprising a plurality of sense amplifier columns and a plurality of memory cells capable of establishing continuity with one of the sense amplifier columns.
2. Description of the Background Art
A DRAM comprising a plurality of memory arrays and a plurality of sense amplifier columns has already been known. In conventional DRAM, the plurality of memory arrays and the plurality of sense amplifier columns are arranged alternately. Each memory array comprises a plurality of memory cells arranged two-dimensionally, and each sense amplifier column comprises a plurality of sense amplifiers arranged in a columnar direction of the memory arrays. A plurality of bit lines are provided between the memory arrays and the sense amplifier columns. Each bit line is provided for each row of the memory arrays. The plurality of memory cells pertaining to each row of memory arrays are connected to a sense amplifier by way of a same bit line.
FIG. 5 shows a portion of conventional DRAM. More particularly, FIG. 5 shows portions of two sense amplifier columns 10 and 12 as well as a portion of a memory array 14 interposed between the sense amplifier columns. Each of the sense amplifier columns 10 and 12 comprises a plurality of circuits which are equal in configuration to sense amplifiers 16 and 18 depicted in the drawing and are arranged in a columnar direction (i.e., in a vertical direction in FIG. 5). In the memory array 14, there is provided a plurality of memory cells two-dimensionally, each of which being capable of conduction with one of the sense amplifier columns 10 and 12.
The sense amplifier 16 comprises a pair of P-type MOS transistors 20 and 22 as well as a pair of N-type MOS transistors 24 and 26. The P-type MOS transistors 20 and 22 are connected to the power source by way of another P-type MOS transistor 28 (referred to as an "activating transistor 28" hereunder). Further, the N-type MOS transistors 24 and 26 are grounded by way of another N-type MOS transistor 30 (referred to as an "activating transistor 30" hereunder).
The activating transistors 28 and 30 receive at their gate terminals activation signals SOP or SON, respectively. The activation signal SOP changes from a high level to a low level when the sense amplifier 16 is required to be active. The activation signal SON changes from a low level to a high level when the sense amplifier 16 is required to be active. The sense amplifier 16 is brought into activation or inactivation upon receipt of the activation signals SON and SOP.
The P-type MOS transistor 22 and the N-type transistor 26 are connected to a signal input line 32 and a signal transmission line 34 at their gate terminals. The signal input line 32 is connected to a bit line (BL) 40 by way of a bit-line selection transistor 36, and to a bit line (BL) 42 by way of a bit-line selection transistor 38. In contrast, the signal transmission line 34 is connected to a data line (DATA) 45 by way of a data line connection transistor 44.
Likewise, the P-type MOS transistor 20 and the N-type transistor 24 are connected to a signal input line 46 and a signal transmission line 47 at there gate terminals. The signal input line 46 is connected to a bit line (/BL) 52 by way of a bit-line selection transistor 48 and to a bit line (/BL) 54 by way of a bit-line selection transistor 50, respectively. In contrast, the signal transmission line 47 is connected to a data (/DATA) line 58 by way of a data line connection transistor 56. The DATA line 45 and the /DATA line 58 will be generically referred to as a "DATA lines pair 45 and 58."
The bit lines BL40 and /BL52 are capable of conduction with a memory array (not shown) provided on the left side of the sense amplifier column 10. In contrast, the bit lines BL42 and /BL54 are capable of conduction with the memory array 14 provided on the right side of the sense amplifier column 10. The bit lines BL40 and /BL52 will be referred generically to as a "bit lines pair 40 and 52", and the bit lines BL42 and /BL54 will be generically referred to as a "bit lines pair 42 and 54."
The sense amplifier columns 10 and 12 have equal configurations. More specifically, the sense amplifier column 12 comprises a bit lines pair 40' and 52' which connect the sense amplifier 18 to the memory array 14 provided on the left side of the sense amplifier 18; and the data line connection transistors 44' and 56' interposed between the sense amplifier 18 and the DATA lines pair 45' and 58'.
A plurality of memory cell columns included in the memory array 14 are divided into a first group of columns and a second group of columns. The first group of columns are connected to the sense amplifier column 10 while the second group of columns are connected to the sense amplifier column 12. More particularly, each of the bit lines BL42 and /BL54 shown in FIG. 5 connected to the sense amplifier column 10 is connected to a plurality of cells which pertain to the same row within the memory array 14 and pertain to the first column group. Further, each of the bit lines BL40' and /BL52' shown in FIG. 5 connected to the sense amplifier column 12 is connected to a plurality of cells which pertain to the same row within the memory array 14 and pertain to the second column group.
A row selection signal generation circuit (not shown) is provided at the end of the memory array 14. A plurality of memory cells pertaining to each column of the memory array 14 are connected to the row selection signal generation circuit by way of the same row selection signal line (not shown). It is to be noted that the memory cells connected to the BLs (including BL42) and the counter parts connected to the /BLs (including /BL50) are connected to the row selection generation circuit by way of different row selection signal lines, respectively. The memory cell becomes able to read and write data upon receipt of a row selection signal from the row signal selection circuit.
The conventional DRAM comprises a column selection line 60. The column selection line 60 is connected to the data line connection transistors 44 and 56 provided to the sense amplifier column 10, as well as to the data line connection transistors 44 and 56 provided to the sense amplifier column 12. The DRAM comprises a plurality of sense amplifier columns arranged in parallel with the sense amplifier columns 10 and 12. These sense amplifier columns have data line connection transistors 44' and 56' as the sense amplifier columns 10 and 12 have. The column selection line 60 is connected to all the sense amplifiers arranged along the same row by way of the data line connection transistors 44 and 56.
The DRAM has column selection lines analogous to the line 60 for the individual rows of sense amplifiers. These column selection lines are connected to column selection signal generation circuit (not shown). Upon receipt of a column address signal from the outside, the column selection signal generation circuit outputs a column selection signal to a column selection line corresponding to the address.
The read operation of the conventional DRAM will now be described. In a case where read operation is requested to the DRAM, a row address is imparted to the DRAM. When the row address signal is imparted to the DRAM as mentioned above, the row selection signal generation circuit to be processing the address generates a row selection signal corresponding to the address. As a result, the row selection signal is supplied to all the memory cells pertaining to the column designated by the address.
The memory cells of the memory array 14 output data to the bit lines corresponding to the respective cells when receiving to the row selection signal. At the same time, the BLs and /BLs to which no data is supplied from the memory cells are maintained at a predetermined reference potential. More specifically, when the column capable of conduction with the bit line BL42 or /BL54 is designated by the row selection signal, the memory array 14 outputs data to a plurality of bit lines including BL42 or a plurality of bit lines including /BL54. Similarly, when a column capable of conduction with the bit line BL40 or /BL52 is designated by a row selection signal, data are output from the memory array 14 to the bit lines corresponding to the activated memory cells of the memory array. While one of bit lines 42, 54, 40' and 52' is receiving the data in the manner described above, other three bit lines are controlled to the reference potential.
During the read operation, either a plurality of transistor pairs (including a pair of transistors 38, 50) provided on the left side of the memory array 14 or a plurality of transistor pairs (including a pair of transistors 36', 48') provided on the right side of the memory array 14 are activated. In the foregoing processing, which is to be activated the right-side transistor pairs or the left-side transistor pairs is decided on the basis of the column designated by the row selection signal.
The following explanation will describe a case where a column capable of conduction with the bit line BL42 is designated. Under the conditions described previously, the data are output from the memory cells to a plurality of bit lines including the bit line BL42. In this case, the transistor pairs (including the pair of transistors 38, 50) provided on the left side of the memory cell 14 are activated. As a result, the signal input line 32 is supplied with data from the memory cells, whereas the signal input line 46 is fed with a reference potential.
The memory cell outputs the electric charge stored therein to the bit line. When the data represent "1," the memory cell changes the potential of the bit line toward predetermined potential Vcc by only .DELTA.V. In contrast, when the data represent "0," the memory cell changes the potential of the bit line toward ground level potential Vss by only AV. The reference potentials for the bit lines BL42, /BL54, BL40, and /BL52 are set to Vcc/2. Accordingly, under the foregoing conditions, after activation of the bit line selection transistors 38 and 50, the signal input line 32 receives (Vcc/2)+.DELTA.V or (Vcc/2)-.DELTA.V while the signal input line 46 receives Vcc/2.
The activating transistors 28 and 30 are brought into activation subsequent to the foregoing processing. When both the activating transistors 28 and 30 are activated, the sense amplifier 15 amplifies a potential difference between the signal input liens 32 and 46 and outputs the thus-amplified potential difference to the signal transmission lines pair 34 and 47. As a result, there appears potential difference corresponding to the data of the memory cells between all the signal transmission line pairs provided to the sense amplifier column 10. Hereinafter, the operations performed to implement the state describe above will be referred to as a "sense operation."
During the read operation, a column address signal is input to the column selection signal generation circuit after the sense operation. Where the column address corresponds to the column selection line 60, the column selection signal generation circuit activates the column selection line 60. When the column selection line 60 is activated, all the data line connection transistors (including the transistors 44, 56) connected to the line 60 are turned on.
At the time when the column selection line 60 is brought into activation, the signal transmission lines pair 34 and 47 connected to the sense amplifier 16 is fed with signals corresponding to the data of the memory cell. In contrast, at the same time, the signal transmission lines pairs connected to other data line connection transistors are held at high impedance. Accordingly, when the column selection line 60 is activated in the manner as mentioned previously, there appear only to the DATA lines 45 and 58 the signals fed to the signal transmission lines pair 34 and 47. As mentioned above, the DRAM outputs data of a memory cell to the DATA lines 45 and 58 when the memory cell is designated by its row and column addresses.
An effective measure to increase the operating speed of the DRAM is to divide the memory cells pertaining to the same memory block into a plurality of banks and to activate the banks in an asynchronous manner. However, when a plurality of banks are operated in an asynchronous manner, a bank which has already completed a sense operation may be requested to be operative while another bank is performing a sense operation. In this case, a column selection line connected to the plurality of banks including the later bank is brought into activation.
When the column selection line is brought into activation, all the sense amplifiers connected to the column selection line, i.e., a plurality of sense amplifiers including the sense amplifier which is currently performing the sense operation, are brought into conduction with the DATA lines. Under these circumstances, the signal output from the sense amplifier which has been already finished the sense operation may be supplied to the sense amplifier which is currently performing a sense operation. If a signal is supplied from the DATA line to the sense amplifier which is currently performing a sense operation, the data supplied to the sense amplifier from the memory cell may be damaged. For this reason, in the conventional DRAM, it has been difficult to form a plurality of banks within the same memory block and to operate the banks in an asynchronous manner.